Semiconductor Dynamic Random Access Memory (DRAM) devices have many memory cells. Indeed, a memory cell is provided for each bit stored by a DRAM device. Each memory cell typically consists of a storage capacitor and an access transistor. Either the source or drain of the access transistor is connected to one terminal of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connection lines called a bit line and a word line, respectively.
In the recent years, there has been increasing density in semiconductor devices leading to decreased size. Each bit of data is stored in a capacitor of a memory cell. Thus, as the DRAMs are scaled down in dimensions, it is a challenge to maintain a sufficiently high stored charge per capacitor. If conventional planar capacitors are used, as the memory cells decrease in size, the area of the capacitors also decrease, resulting in a reduction of cell capacitance. For very small memory cells, planar capacitors become very difficult to use reliably. Further, this results in the capacitor being very susceptible to .alpha. particle interference. Additionally, as the capacitance decreases, the charge held by storage capacitor must be refreshed often.
Thus, for DRAMs, there have been disclosed various structures suitable for miniaturization of the device. Both a trench capacitor formed in a substrate and a stacked capacitor formed over a substrate are being used for DRAM application. The stacked memory cell in which the storage node is formed above a silicon substrate is suitable for high density integrated circuits. Further, the shape of the capacitor can be controlled to increase the capacitance without increasing the area it occupies the substrate. It also exhibits the advantages of being less likely to cause soft errors. However, the trench capacitor is susceptible to the well-known leakage problem. This makes the stacked capacitor very popular for making the DRAMs.
Prior art approaches to overcome these problems have resulted in the development of capacitors having roughened surfaces forming the electrodes. See, for example, M. Sakao et I., "CAPACITOR-OVER-BIT-LINE (COB) CELL WITH A HEMISPHERICAL-GRAIN STORAGE NODE FOR 64 Mb DRAM" in IEDM 1990 technical digest pp. 655-658. In U.S. Pat. No. 5,278,091 to P. Fazan, Fazan proposed a crown stacked capacitor with HSG (HemiSpherical Grain) rugged polysilicon on storage node.
In general, the HSG-Si is deposited by low pressure chemical vapor deposition method at the transition temperature from amorphous Si to polycrystalline Si. This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node. The HSG-Si storage node can be fabricated by addition of two process steps, i.e., HSG-Si deposition and an etchback step. A further HSG-Si electrode node has been proposed, please refer to "NEW CYLINDRICAL CAPACITOR USING HEMISPHERICAL GRAIN Si FOR 256 Mb DRAMs", H. Watanabe et 1., microelectronics research laboratories, NEC Corporation.